This invention relates to a process for manufacturing thin film transistors that have small source-drain areas, small gate-source parasitic capacitance C.sub.gs, and low contact resistance. Such thin film transistors can be used as active matrices for flat panel liquid crystal displays.
Various known techniques for making thin film transistors lead inevitably to an overlap of the transistor gate with the source and drain. This overlap introduces gate-source parasitic capacitance. This capacitance is particularly prejudicial to the operation of thin film transistor made of hydrogenated amorphous silicon, because it increases the response time of the transistors and introduces unacceptable DC voltage levels when the transistors are used in a liquid crystal display device. This parasitic capacitance must consequently be minimized.
A manufacturing process for thin layer transistors has been disclosed in "A Self-Alignment Process for Amorphous Silicon Thin Film Transistors", IEEE Electron Device Letters, Vol. EDL3, No. 7, July, 1982. This process enables the gate of the transistor to be self-aligned with the drain and source to eliminate the overlap capacitance almost entirely. This manufacturing process is too complex, however, to be employed in mass production. A device made by this process is also not "electrically" coplanar, i.e., the channel and the drain and source electrodes of the transistors are not in the same plane. Since the source and drain are in "Schottky contact" with the channel, its "on" current is degraded because of the high series resistance.
Another self-aligned thin film transistor manufacturing process is disclosed in U.S. Pat. No. 4,587,720, "Process for the Manufacture of a Self-Aligned Thin-Film Transistor", Andre Chenvas-Paule and Bernard Diem, May 13, 1986. This process produces a coplanar, ohmic source-drain a-Si TFT. A lift-off method is used to form the source and drain with a channel/n+ a-Si layer ohmic contact. The n+ a-Si layer is grown in a Plasma Enhanced Chemical Vapor Deposition (PECVD) system, thereby necessitating the use of a high temperature photoresist material. Because using PECVD film possesses good step coverage, it will cause difficulty while executing the lift-off process. In other words, the lift-off process for n+ a-Si is hard to achieve and results in a drastically decreased yield of TFT arrays. Therefore, this process cannot be satisfactorily employed in the manufacture of large area flat panel displays.
Furthermore, both of the above methods for manufacturing self-aligned TFT's need a very thin a-Si film, e.g., 20 nm, for exposing the positive photoresist layer to the Hg lamp. Poor uniformity in the thickness of this very thin film causes the yield of large area flat panel displays to decrease drastically.
Recently, a high yield inverted staggered a-Si TFT has been developed by Matsushita Electric Industry Co., Ltd. This process is described in an article in Japan Display, 1986, entitled "12.5" LCD Addressed by a-Si TFT's Employing Redundancy Technology", M. Takeda et al. In this disclosure, an SiN gate insulating layer, an a-Si film active semiconductor and an SiN top passivation layer are successively deposited in the same pumpdown time, using different kinds of gases. This technique is effective in eliminating contamination at the gate insulating layer/a-Si film interface, where the channel region of TFT is formed. The top passivation layer provides a good passivation of the active a-Si film from successive wet processes, and is also used as an autostopper when patterning the source-drain n+ contact layer. Because the channel, the source and the drain are not in the same plane, this kind of device is a staggered TFT. This fabrication method needs a large source-drain contact region, however, to reduce drain-current crowding effect, and hence the parasitic capacitance of a device formed by this method is unavoidably large.